(1) Field of the Invention
The present invention relates in general to integrated circuits and more particularly to the manufacture of a device of the SOI (Silicon On Insulator) type comprising a layer of semiconductor material on a layer of insulating material.
(2) Description of the Related Art
The manufacture of SOI (Silicon On Insulator) devices comprising a layer of semiconductor material on a layer of insulating material is known. These SOI-type devices are more particularly intended to be used for producing devices of the type which are fully depleted of charge carriers in the channel region, also called fully-depleted devices, in which the thickness of the silicon-containing semiconductor substrate, also called the active layer, defines inter alia the threshold voltage of MOS-type transistors and is of great importance.
A major difficulty in the use of fully-depleted assemblies is how to produce thin layers of silicon-containing semiconductor substrate, on a layer of an insulating material with good control and sufficient reproducibility of the thickness of this active layer between two different manufacturing batches.
To perform properly, fully-depleted structures require active layers with a thickness of about 5 to 30 nanometers depending on the threshold voltage that it is desired to obtain and on the transistor gate dimensions. For example, for 0.1 μm technology, the ideal silicon thickness is about 15 nm for a threshold voltage of around 0.35 volts. Any deviation from planarity of the active layer and any difference in thickness of the active layer between two manufacturing batches result in a corresponding variation in the threshold voltage. In general, on any given active layer, the deviation from planarity is small (about a few percent), but from one batch to another the difference in thickness may be much greater.
The known techniques for fabricating SOI-type devices all have a number of drawbacks, particularly a low production yield, the formation of relatively thick active layers, of mediocre uniformity and difficult to reproduce from one assembly to another, and consequently having a threshold voltage that cannot be easily controlled.
One first SOI-type device fabrication process, known as “SIMOX” technology, consists in forming an SiO2 layer buried in a silicon substrate by a step of high-dose oxygen implantation followed by annealing at a temperature above 1300° C. The drawbacks of this process are in particular the high cost of fabricating the trenches, the crystal defects generated in the silicon layer by high-dose, high-energy oxygen implantation, the small thickness of the buried insulation layer and the defects (holes) within the buried insulation layer.
Finally, this process, because the thicknesses of the silicon and buried silicon oxide layers are determined by the implantation process, that is to say a massive implantation of oxygen at high energy and with a high dose, makes it difficult to achieve thicknesses of less than 50 nm in the case of the thin residual silicon layer.
A second process, known as “BESOI” technique consists in producing an SOI-type device by forming, on a surface of a first silicon substrate, a thin SiO2 film, joining this first substrate, via the thin SiO2 film, to a second silicon substrate and finally removing, by mechanical grinding and polishing, part of one of the silicon substrates in order to form a thin silicon layer above the buried silicon oxide layer. The silicon oxide layer on the first silicon substrate is formed by a succession of steps which are: oxidation of the surface of this first substrate and then the etching of the oxide layer formed in order to obtain the desired thickness.
This process makes it possible to obtain only buried silicon oxide layers and silicon layers on the buried silicon oxide which are relatively thick because of the poor control of the etching process. Furthermore, the thin layers obtained by this process have poor uniformity as a result of the use of mechanical steps which in general generate ups and downs on the surface of the active layer.
A third process, known as “SMARTCUT” technology, consists in forming a thin silicon oxide layer by oxidation on a first silicon substrate and then implanting, under the thin silicon oxide layer, H+ ions into this first silicon substrate in order to form, within it, a plane of cavities. Next, this first substrate is bonded to a second pre-oxidized silicon substrate via the thin silicon oxide layer. The assembly thus formed is then heat treated for the purpose of converting the plane of cavities into a splitting plane.
This process makes it possible to recover, on the one hand, an SOI assembly and, on the other hand, a reusable silicon substrate and it requires the implantation of a high dose of hydrogen atoms. Despite the use of hydrogen atoms which are smaller in size than the oxygen atoms of the SIMOX process, the surface of the thin silicon layer obtained is also damaged. Furthermore, the use of this technique does not in general make it possible to obtain thin silicon layer thicknesses of less than approximately 50 nm. In the SOI assemblies thus obtained, the thickness of the silicon active layer formed is determined by the hydrogen implantation, allowing the initial substrate to be cut and this layer then to be finely polished. The deviation from planarity caused by this process is approximately 5 nm, whatever the thickness of the final layer. It therefore becomes a major drawback for thicknesses of less than 50 nm. In addition, the variation in thickness from one wafer to another may be about 25% to 40% of the mean thickness of a batch of wafers, for example in the case of nominal thicknesses of less than 50 nm, thereby constituting a major handicap when producing complex circuits because of the difference in threshold voltage resulting from the difference in thickness.
The above processes are described, in particular, in the article “SOI: Materials to Systems (by A. J. Auberton-Hervé, IEEE, 1996.
According, a need exist to provide a process for fabricating an SOI-type device which overcomes the drawbacks of the processes of the prior art.